tmp_ar            744 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 	sljit_si tmp_ar, base, delay_slot;
tmp_ar            753 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 		tmp_ar = reg_ar;
tmp_ar            756 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 		tmp_ar = DR(TMP_REG1);
tmp_ar            781 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 					FAIL_IF(push_inst(compiler, ADDU_W | S(base) | T(TMP_REG3) | DA(tmp_ar), tmp_ar));
tmp_ar            782 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 					return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | SA(tmp_ar) | TA(reg_ar), delay_slot);
tmp_ar            804 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 				tmp_ar = DR(TMP_REG3);
tmp_ar            807 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 				FAIL_IF(push_inst(compiler, ADDU_W | S(base) | T(!argw ? OFFS_REG(arg) : TMP_REG3) | DA(tmp_ar), tmp_ar));
tmp_ar            808 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 			return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | SA(tmp_ar) | TA(reg_ar), delay_slot);
tmp_ar            877 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 	FAIL_IF(push_inst(compiler, ADDU_W | S(TMP_REG3) | T(base) | DA(tmp_ar), tmp_ar));
tmp_ar            878 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 	return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | SA(tmp_ar) | TA(reg_ar), delay_slot);
tmp_ar           1342 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 	sljit_si tmp_ar, base;
tmp_ar           1351 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 		tmp_ar = reg_ar;
tmp_ar           1353 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 		tmp_ar = TMP_REG1_mapped;
tmp_ar           1387 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 					FAIL_IF(ADD(tmp_ar, reg_map[base], TMP_REG3_mapped));
tmp_ar           1389 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 						return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, tmp_ar);
tmp_ar           1391 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 						return PB2(data_transfer_insts[flags & MEM_MASK], tmp_ar, reg_ar);
tmp_ar           1415 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 				tmp_ar = TMP_REG3_mapped;
tmp_ar           1417 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 				FAIL_IF(ADD(tmp_ar, reg_map[base], reg_map[!argw ? OFFS_REG(arg) : TMP_REG3]));
tmp_ar           1420 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 				return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, tmp_ar);
tmp_ar           1422 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 				return PB2(data_transfer_insts[flags & MEM_MASK], tmp_ar, reg_ar);
tmp_ar           1525 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 	FAIL_IF(ADD(tmp_ar, TMP_REG3_mapped, reg_map[base]));
tmp_ar           1528 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 		return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, tmp_ar);
tmp_ar           1530 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 		return PB2(data_transfer_insts[flags & MEM_MASK], tmp_ar, reg_ar);