reg_ar            701 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c static sljit_si getput_arg_fast(struct sljit_compiler *compiler, sljit_si flags, sljit_si reg_ar, sljit_si arg, sljit_sw argw)
reg_ar            710 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 			| TA(reg_ar) | IMM(argw), ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) ? reg_ar : MOVABLE_INS));
reg_ar            742 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c static sljit_si getput_arg(struct sljit_compiler *compiler, sljit_si flags, sljit_si reg_ar, sljit_si arg, sljit_sw argw, sljit_si next_arg, sljit_sw next_argw)
reg_ar            753 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 		tmp_ar = reg_ar;
reg_ar            754 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 		delay_slot = reg_ar;
reg_ar            763 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 		if ((flags & WRITE_BACK) && reg_ar == DR(base)) {
reg_ar            764 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 			SLJIT_ASSERT(!(flags & LOAD_DATA) && DR(TMP_REG1) != reg_ar);
reg_ar            765 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 			FAIL_IF(push_inst(compiler, ADDU_W | SA(reg_ar) | TA(0) | D(TMP_REG1), DR(TMP_REG1)));
reg_ar            766 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 			reg_ar = DR(TMP_REG1);
reg_ar            773 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 					return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot);
reg_ar            779 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 						return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot);
reg_ar            782 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 					return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | SA(tmp_ar) | TA(reg_ar), delay_slot);
reg_ar            788 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 					return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(base) | TA(reg_ar), delay_slot);
reg_ar            808 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 			return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | SA(tmp_ar) | TA(reg_ar), delay_slot);
reg_ar            811 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 		return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(base) | TA(reg_ar), delay_slot);
reg_ar            816 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 		if (reg_ar == DR(base)) {
reg_ar            817 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 			SLJIT_ASSERT(!(flags & LOAD_DATA) && DR(TMP_REG1) != reg_ar);
reg_ar            819 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 				FAIL_IF(push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(base) | TA(reg_ar) | IMM(argw), MOVABLE_INS));
reg_ar            824 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 			FAIL_IF(push_inst(compiler, ADDU_W | SA(reg_ar) | TA(0) | D(TMP_REG1), DR(TMP_REG1)));
reg_ar            825 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 			reg_ar = DR(TMP_REG1);
reg_ar            847 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 		return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(base) | TA(reg_ar), delay_slot);
reg_ar            855 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 		return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot);
reg_ar            869 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 		return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot);
reg_ar            874 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 		return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot);
reg_ar            878 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 	return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | SA(tmp_ar) | TA(reg_ar), delay_slot);
reg_ar            881 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c static SLJIT_INLINE sljit_si emit_op_mem(struct sljit_compiler *compiler, sljit_si flags, sljit_si reg_ar, sljit_si arg, sljit_sw argw)
reg_ar            883 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 	if (getput_arg_fast(compiler, flags, reg_ar, arg, argw))
reg_ar            887 ext/pcre/pcrelib/sljit/sljitNativeMIPS_common.c 	return getput_arg(compiler, flags, reg_ar, arg, argw, 0, 0);
reg_ar           1288 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c static sljit_si getput_arg_fast(struct sljit_compiler *compiler, sljit_si flags, sljit_si reg_ar, sljit_si arg, sljit_sw argw)
reg_ar           1301 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			FAIL_IF(PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, ADDR_TMP_mapped));
reg_ar           1303 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			FAIL_IF(PB2(data_transfer_insts[flags & MEM_MASK], ADDR_TMP_mapped, reg_ar));
reg_ar           1340 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c static sljit_si getput_arg(struct sljit_compiler *compiler, sljit_si flags, sljit_si reg_ar, sljit_si arg, sljit_sw argw, sljit_si next_arg, sljit_sw next_argw)
reg_ar           1351 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 		tmp_ar = reg_ar;
reg_ar           1360 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 		if ((flags & WRITE_BACK) && reg_ar == reg_map[base]) {
reg_ar           1361 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			SLJIT_ASSERT(!(flags & LOAD_DATA) && reg_map[TMP_REG1] != reg_ar);
reg_ar           1362 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			FAIL_IF(ADD(TMP_REG1_mapped, reg_ar, ZERO));
reg_ar           1363 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			reg_ar = TMP_REG1_mapped;
reg_ar           1371 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 						return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, TMP_REG3_mapped);
reg_ar           1373 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 						return PB2(data_transfer_insts[flags & MEM_MASK], TMP_REG3_mapped, reg_ar);
reg_ar           1382 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 							return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, TMP_REG3_mapped);
reg_ar           1384 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 							return PB2(data_transfer_insts[flags & MEM_MASK], TMP_REG3_mapped, reg_ar);
reg_ar           1389 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 						return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, tmp_ar);
reg_ar           1391 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 						return PB2(data_transfer_insts[flags & MEM_MASK], tmp_ar, reg_ar);
reg_ar           1397 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 						return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, reg_map[base]);
reg_ar           1399 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 						return PB2(data_transfer_insts[flags & MEM_MASK], reg_map[base], reg_ar);
reg_ar           1420 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 				return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, tmp_ar);
reg_ar           1422 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 				return PB2(data_transfer_insts[flags & MEM_MASK], tmp_ar, reg_ar);
reg_ar           1428 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, reg_map[base]);
reg_ar           1430 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			return PB2(data_transfer_insts[flags & MEM_MASK], reg_map[base], reg_ar);
reg_ar           1435 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 		if (reg_ar == reg_map[base]) {
reg_ar           1436 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			SLJIT_ASSERT(!(flags & LOAD_DATA) && TMP_REG1_mapped != reg_ar);
reg_ar           1440 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 					FAIL_IF(PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, ADDR_TMP_mapped));
reg_ar           1442 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 					FAIL_IF(PB2(data_transfer_insts[flags & MEM_MASK], ADDR_TMP_mapped, reg_ar));
reg_ar           1450 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			FAIL_IF(ADD(TMP_REG1_mapped, reg_ar, ZERO));
reg_ar           1451 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			reg_ar = TMP_REG1_mapped;
reg_ar           1476 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, reg_map[base]);
reg_ar           1478 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			return PB2(data_transfer_insts[flags & MEM_MASK], reg_map[base], reg_ar);
reg_ar           1490 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, TMP_REG3_mapped);
reg_ar           1492 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			return PB2(data_transfer_insts[flags & MEM_MASK], TMP_REG3_mapped, reg_ar);
reg_ar           1509 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, TMP_REG3_mapped);
reg_ar           1511 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			return PB2(data_transfer_insts[flags & MEM_MASK], TMP_REG3_mapped, reg_ar);
reg_ar           1520 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, TMP_REG3_mapped);
reg_ar           1522 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 			return PB2(data_transfer_insts[flags & MEM_MASK], TMP_REG3_mapped, reg_ar);
reg_ar           1528 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 		return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, tmp_ar);
reg_ar           1530 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 		return PB2(data_transfer_insts[flags & MEM_MASK], tmp_ar, reg_ar);
reg_ar           1533 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c static SLJIT_INLINE sljit_si emit_op_mem(struct sljit_compiler *compiler, sljit_si flags, sljit_si reg_ar, sljit_si arg, sljit_sw argw)
reg_ar           1535 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 	if (getput_arg_fast(compiler, flags, reg_ar, arg, argw))
reg_ar           1540 ext/pcre/pcrelib/sljit/sljitNativeTILEGX_64.c 	return getput_arg(compiler, flags, reg_ar, arg, argw, 0, 0);