shift2             32 ext/pcre/pcrelib/sljit/sljitNativeMIPS_64.c 	sljit_si shift2;
shift2             94 ext/pcre/pcrelib/sljit/sljitNativeMIPS_64.c 	shift2 = shift - 16;
shift2             97 ext/pcre/pcrelib/sljit/sljitNativeMIPS_64.c 		shift2 -= 4;
shift2            102 ext/pcre/pcrelib/sljit/sljitNativeMIPS_64.c 		shift2 -= 2;
shift2            107 ext/pcre/pcrelib/sljit/sljitNativeMIPS_64.c 		shift2--;
shift2            111 ext/pcre/pcrelib/sljit/sljitNativeMIPS_64.c 	SLJIT_ASSERT((uimm & 0x8000000000000000l) && (shift2 > 0) && (shift2 <= 16));
shift2            113 ext/pcre/pcrelib/sljit/sljitNativeMIPS_64.c 	FAIL_IF(push_inst(compiler, DSLL | TA(dst_ar) | DA(dst_ar) | SH_IMM(shift - shift2), dst_ar));
shift2            115 ext/pcre/pcrelib/sljit/sljitNativeMIPS_64.c 	FAIL_IF(push_inst(compiler, DSLL | TA(dst_ar) | DA(dst_ar) | SH_IMM(shift2), dst_ar));
shift2            117 ext/pcre/pcrelib/sljit/sljitNativeMIPS_64.c 	imm &= (1l << shift2) - 1;
shift2             49 ext/pcre/pcrelib/sljit/sljitNativePPC_64.c 	sljit_uw shift2;
shift2             99 ext/pcre/pcrelib/sljit/sljitNativePPC_64.c 	ASM_SLJIT_CLZ(tmp2, shift2);
shift2            100 ext/pcre/pcrelib/sljit/sljitNativePPC_64.c 	tmp2 <<= shift2;
shift2            104 ext/pcre/pcrelib/sljit/sljitNativePPC_64.c 		shift2 += 15;
shift2            105 ext/pcre/pcrelib/sljit/sljitNativePPC_64.c 		shift += (63 - shift2);
shift2            108 ext/pcre/pcrelib/sljit/sljitNativePPC_64.c 		return PUSH_RLDICR(reg, shift2);