reg2               63 ext/pcre/pcrelib/sljit/sljitNativeARM_T2_32.c #define IS_2_LO_REGS(reg1, reg2) \
reg2               64 ext/pcre/pcrelib/sljit/sljitNativeARM_T2_32.c 	(reg_map[reg1] <= 7 && reg_map[reg2] <= 7)
reg2               65 ext/pcre/pcrelib/sljit/sljitNativeARM_T2_32.c #define IS_3_LO_REGS(reg1, reg2, reg3) \
reg2               66 ext/pcre/pcrelib/sljit/sljitNativeARM_T2_32.c 	(reg_map[reg1] <= 7 && reg_map[reg2] <= 7 && reg_map[reg3] <= 7)
reg2             91781 ext/sqlite3/libsqlite/sqlite3.c     int reg1, reg2, reg3;
reg2             91794 ext/sqlite3/libsqlite/sqlite3.c     reg2 = pParse->regRoot = ++pParse->nMem;
reg2             91818 ext/sqlite3/libsqlite/sqlite3.c       sqlite3VdbeAddOp2(v, OP_Integer, 0, reg2);
reg2             91822 ext/sqlite3/libsqlite/sqlite3.c       pParse->addrCrTab = sqlite3VdbeAddOp2(v, OP_CreateTable, iDb, reg2);