reg1               63 ext/pcre/pcrelib/sljit/sljitNativeARM_T2_32.c #define IS_2_LO_REGS(reg1, reg2) \
reg1               64 ext/pcre/pcrelib/sljit/sljitNativeARM_T2_32.c 	(reg_map[reg1] <= 7 && reg_map[reg2] <= 7)
reg1               65 ext/pcre/pcrelib/sljit/sljitNativeARM_T2_32.c #define IS_3_LO_REGS(reg1, reg2, reg3) \
reg1               66 ext/pcre/pcrelib/sljit/sljitNativeARM_T2_32.c 	(reg_map[reg1] <= 7 && reg_map[reg2] <= 7 && reg_map[reg3] <= 7)
reg1             91781 ext/sqlite3/libsqlite/sqlite3.c     int reg1, reg2, reg3;
reg1             91793 ext/sqlite3/libsqlite/sqlite3.c     reg1 = pParse->regRowid = ++pParse->nMem;
reg1             91825 ext/sqlite3/libsqlite/sqlite3.c     sqlite3VdbeAddOp2(v, OP_NewRowid, 0, reg1);
reg1             91827 ext/sqlite3/libsqlite/sqlite3.c     sqlite3VdbeAddOp3(v, OP_Insert, 0, reg3, reg1);